View FXMA2102UMX_839171.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

november 2010 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications fxma2102 dual supply, 2-bit voltage translator / buffer / repeater / isolator for i 2 c applications features ? bi-directional interface between any two levels: 1.65v to 5.5v ? direction control not needed ? system gpio resources not required when oe tied to v cca ? i 2 c 400pf buffer / repeater ? i 2 c bus isolation ? a/b port v ol = 175mv (typical), v il = 150mv, i ol = 6ma ? open-drain inputs / outputs ? accommodates standard-mode and fast-mode i 2 c-bus devices ? supports i 2 c clock stretching & multi-master ? fully configurable: inputs and outputs track v cc ? non-preferential power-up; either v cc may be powered-up first ? outputs switch to 3-state if either v cc is at gnd ? tolerant output enable: 5v ? packaged in 8-terminal leadless micropak? (1.6mm x 1.6mm) and ultrathin mlp (1.2mm x 1.4m) ? esd protection exceeds: - 8kv hbm esd (per jesd22-a114) - 2kv cdm (per jesd22-c101) description the fxma2102 is a high-performance configurable dual-voltage-supply translator for bi-directional voltage translation over a wide range of input and output voltages levels. intended for use as a voltage translator in applications using the i 2 c bus interface, the input and output voltage levels are compatible with i 2 c device specification voltage levels. external pull- up resistors are required. the device is designed so that the a port tracks the v cca level and the b port tracks the v ccb level. this allows for bi-directional a/b port voltage translation between any two levels from 1.65v to 5.5v. v cca can equal v ccb from 1.65v to 5.5v. either v cc can be powered-up first. internal power-down control circuits place the device in 3-state if either v cc is removed. the two ports of the device have automatic direction sense capability. either port may sense an input signal and transfer it as an output signal to the other port. ordering information part number operating temperature range top mark package packing method fxma2102l8x -40 to +85c xn 8-lead micropak?, 1.6mm wide 5000 units on tape and reel FXMA2102UMX 8-lead ultrathin mlp, 1.2mm x 1.4mm
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 2 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications block diagram figure 1. block diagram, 1 of 2 channels
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 3 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications pin configuration a 0 a 1 gnd 765 123 84 oe v cca v ccb b 0 b 1 figure 2. micropak? ( top-through view) figure 3. umlp (top-through view) pin definitions pin # name description 1 v cca a-side power supply 2, 3 a 0 , a 1 a-side inputs or 3-state outputs 4 gnd ground 5 oe output enable input 6, 7 b 1 , b 0 b-side inputs or 3-state outputs 8 v ccb b-side power supply truth table control outputs oe low logic level 3-state high logic level normal operation note: 1. if the oe pin is driven low, the fxma2102 is disabled and the a 0 , a 1 , b 0 , and b 1 pins (including dynamic drivers) are forced into 3-state.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 4 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v cca , v ccb supply voltage ?0.5 7.0 v v in dc input voltage a port ?0.5 7.0 b port ?0.5 7.0 control input (oe) ?0.5 7.0 v o output voltage (2) a n outputs 3-state ?0.5 7.0 v b n outputs 3-state ?0.5 7.0 a n outputs active ?0.5 v cca + 0.5v b n outputs active ?0.5 v ccb + 0.5v i ik dc input diode current at v in < 0v ?50 ma i ok dc output diode current at v o < 0v ?50 ma at v o > v cc +50 i oh / i ol dc output source/sink current ?50 +50 ma i cc dc v cc or ground current per supply pin 100 ma p d power dissipation at 400khz 0.129 mw t stg storage temperature range ?65 +150 c esd electrostatic discharge capability human body model, jesd22-a114 8 kv charged device mode, jesd22-c101 2 note: 2. i o absolute maximum rating must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v cca , v ccb power supply operating 1.65 5.50 v v in input voltage a port 0 5.5 v b port 0 5.5 control input (oe) 0 v cca ja thermal resistance 8-lead micropak? 279.0 c/w 8-lead ultrathin mlp 301.5 t a free air operating temperature ?40 +85 c note: 3. all unused inputs and i/o pins must be held at v cci or gnd.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 5 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications functional description power-up/power-down sequencing fxm translators offer an advantage in that either v cc may be powered up first. this benefit derives from the chip design. when either v cc is at 0v, outputs are in a high-impedance state. the control input (oe) is designed to track the v cca supply. a pull-down resistor tying oe to gnd should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. the size of the pull-down resistor is based upon the current-sinking capability of the device driving the oe pin. the recommended power-up sequence is: 1. apply power to the first v cc . 2. apply power to the second v cc . 3. drive the oe input high to enable the device. the recommended power-down sequence is: 1. drive oe input low to disable the device. 2. remove power from either v cc . 3. remove power from other v cc . note: 4. alternatively, the oe pin can be hardwired to v cca to save gpio pins. if oe is hardwired to v cca , either v cc can be powered up or down first. application circuit figure 4. application circuit
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 6 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications application notes the fxma2102 has open-drain i/os and requires external pull-up resistors on the four data i/o pins, as shown in figure 4. if a pair of data i/o pins (a n /b n ) is not used, both pins should be tied to gnd (or both to v cc ). in this case, pull-down or pull-up resistors are not required. the recommended values for the pull-up resistors (rpu) are 1k ? to 10k ? ; however, depending on the total bus capacitance, the user is free to vary the pull-up resistor value to meet the maximum i 2 c edge rate per the i 2 c specification (um10204 rev. 03, june 19, 2007). for example, the maximum edge rate (30% - 70%) during fast mode ( 400kbit/s) is 300ns. if bus capacitance is approaching the maximum 400pf, lower the rpu value to keep the rise time below 300ns (fast mode). section 7.1 of the i 2 c specification provides an excellent guideline for pull-up resistor sizing. theory of operation the fxma2102 is designed for high-performance level shifting and buffer / repeating in an i 2 c application. figure 1 shows that each bi-directional channel contains two series-npa ssgates and two dynamic drivers. this hybrid architecture is highly beneficial in an i 2 c application where auto-direction is a necessity. for example, during the following three i 2 c protocol events: ? clock stretching ? slave?s ack bit (9 th bit = 0) following a master?s write bit (8 th bit = 0) ? clock synchronization and multi master arbitration the bus direction needs to change from master to slave to slave to master without the occurrence of an edge. if there is an i 2 c translator between the master and slave in these examples, the i 2 c translator must change direction when both a and b ports are low. the npassgates can accomplish this task very efficiently because, when both a and b ports are low, the npassgates act as a low resistive short between the two (a and b) ports. due to i 2 c?s open-drain topology, i 2 c masters and slaves are not push/pull drivers. logic lows are ?pulled down? (i sink ), while logic highs are ?let go? (3- state). for example, when the master lets go of scl (scl always comes from the master), the rise time of scl is largely determined by the rc time constant, where r = r pu and c = the bus capacitance. if the fxma2102 is attached to the master [on the a port] in this example, and there is a slave on the b port, the npassgates act as a low resistive short between both ports until either of the port?s v cc /2 thresholds are reached. after the rc time constant has reached the v cc /2 threshold of either port, the port?s edge detector triggers both dynamic drivers to drive their respective ports in the low-to-high (lh) direction, accelerating the rising edge. the resulting rise time resembles the scope shot in figure 5. effectively, two distinct slew rates appear in rise time. the first slew rate (slower) is the rc time constant of the bus. the second slew rate (much faster) is the dynamic driver accelerating the edge. if both the a and b ports of the translator are high, a high-impedance path exists between the a and b ports because both the npassgates are turned off. if a master or slave device decides to pull scl or sda low, that device?s driver pulls down (i sink ) scl or sda until the edge reaches the a or b port v cc /2 threshold. when either the a or b port threshold is reached, the port?s edge detector triggers both dynamic drivers to drive their respective ports in the high-to-low (hl) direction, accelerating the falling edge. figure 5. fxma2102 waveform c: 600pf, r pu : 2.2k
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 7 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications buffer / repeater performance the fxma2102 dynamic drivers have enough current sourcing capability to drive a 400pf capacitive bus. this is beneficial for instances when an i 2 c buffer / repeater is required. the i 2 c specification stipulates a maximum bus capacitance of 400pf. if an i 2 c segment exceeds 400pf, an i 2 c buffer / repeater is required to split the segment into two segments, each of which is less than 400pf. figure 5 is a scope shot of an fxma2102 driving a lumped load of 600pf. notice the (30% - 70%) rise time is only 112ns (r pu = 2.2k). this is well below the maximum edge rate of 300ns. not only does the fxma2102 drive 400pf, but it also provides excellent headroom below the i 2 c specification maximum edge rate of 300ns. v ol vs. i ol the i 2 c specification mandates a maximum v il (i ol of 3ma) of v cc ? 0.3 and a maximum v ol of 0.4v. if there is a master on the a port of an i 2 c translator with a v cc of 1.65v and a slave on the i 2 c translator b port with a v cc of 3.3v, the maximum v il of the master is (1.65v x 0.3) 495mv. the slave could legally transmit a valid logic low of 0.4v to the master. if the i 2 c translator?s channel resistance is too high, the voltage drop across the translator could present a v il to the master greater than 495mv. to complicate matters, the i 2 c specification states that 6ma of i ol is recommended for bus capacitances approaching 400pf. more i ol increases the voltage drop across the i 2 c translator. the i 2 c application benefits when i 2 c translators exhibit low v ol performance. figure 6 depicts typical fxma2102 v ol performance vs. the competition, given a 0.4v v il . figure 6. v ol vs. i ol
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 8 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications i 2 c bus isolation the fxma2102 supports i 2 c bus isolation for the following conditions: ? bus isolation if bus clear ? bus isolation if either v cc goes to ground bus clear because the i 2 c specification defines the minimum scl frequency of dc, the scl signal can be held low forever; however, this condition shuts down the i 2 c bus. the i 2 c specification refers to this condition as ?bus clear?. in figure 7, if slave #2 holds down scl forever, the master and slave #1 are not able to communicate, because the fxma2102 passes the scl stuck-low condition from slave #2 to slave #1 as well as the master. however, if the oe pin is pulled low (disabled), both ports (a and b) are 3-stated. this results in the fxma2102 isolating slave #2 from the master and slave #1, allowing full communication between the master and slave #1. either v cc to gnd if slave #2 is a camera that is suddenly removed from the i 2 c bus, resulting in v ccb transitioning from a valid v cc (1.65v ? 5.5v) to 0v, the fxma2102 automatically forces scl and sda on both its a and b ports into 3- state. once v ccb has reached 0v, full i 2 c communication between the master and slave #1 remains undisturbed. master fxma2102 i 2 c buffer translator scl sda slave #2 scl sda v cc = 3.3v slave #1 scl sda v cc = 1.8v v ccb v cca oe oe: high enable low disable v ccb : 3.3v v cc domain v cca : 1.8v v cc domain figure 7. bus isolation
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 9 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications dc electrical characteristics t a = ?40c to +85c. symbol parameter conditions v cca (v) v ccb (v) min. max. units v iha high level input voltage a data inputs a n 1.65?5.50 1.65?5.50 v cca ? 0.4 v control input oe 1.65?5.50 1.65?5.50 0.7 x v cca v ihb high level input voltage b data inputs b n 1.65?5.50 1.65?5.50 v ccb ? 0.4 v v ila low level input voltage a data inputs a n 1.65?5.50 1.65?5.50 0.4 v control input oe 1.65?5.50 1.65?5.50 0.3 x v cca v ilb low level input voltage b data inputs b n 1.65?5.50 1.65?5.50 0.4 v v ol low level output voltage v il = 0.15v 1.65?2.30 1.65?5.50 0.4 v i ol = 6ma i l input leakage current control input oe, v in = v cca or gnd 1.65?5.50 1.65?5.50 1.0 a i off power off leakage current a n v in or v o = 0v to 5.5v 0 5.50 2.0 a b n v in or v o = 0v to 5.5v 5.50 0 2.0 i oz 3-state output leakage (6) a n , b n v o = 0v to 5.5v, oe = v il 5.50 5.50 2.0 a a n v o = 0v to 5.5v, oe = don?t care 5.50 0 2.0 b n v o = 0v to 5.5v, oe = don?t care 0 5.50 2.0 i cca / b quiescent supply current (7,8) v in = v cci or gnd, i o = 0 1.65?5.50 1.65?5.50 5.0 a i ccz quiescent supply current (7) v in = v cci or gnd, i o = 0, oe = v il 1.65?5.50 1.65?5.50 5.0 a i cca quiescent supply current (6) v in = 5.5v or gnd, i o = 0, oe = don?t care, b n to a n 0 1.65?5.50 ?2.0 a 1.65?5.50 0 2.0 i ccb quiescent supply current (6) v in = 5.5v or gnd, i o = 0, oe = don?t care, a n to b n 1.65?5.50 0 ?2.0 a 0 1.65?5.50 2.0 notes: 5. this table contains the output voltage for static condi tions. dynamic drive specificat ions are given in dynamic output electrical characteristics. 6. ?don?t care? indicates any valid logic level. 7. v cci is the v cc associated with the input side. 8. reflects current per supply, v cca or v ccb .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 10 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications dynamic output electrical characteristics output rise / fall time output load: c l = 50pf, r pu = 2.2k , push / pull driver, and t a = -40c to +85c. symbol parameter v cco (10) units 4.5 to 5.5v 3.0 to 3.6v 2.3 to 2.7v 1.65 to 1.95v typ. typ. typ. typ. t rise output rise time; a port, b port (11) 3 4 5 7 ns t fall output fall time; a port, b port (12) 1 1 1 1 ns notes: 9. output rise and fall times guaranteed by design si mulation and characterization; not production tested. 10. v cco is the v cc associated with the output side. 11. see figure 12 . 12. see figure 13 . maximum data rate (13) output load: c l = 50pf, r pu = 2.2k , push / pull driver, and t a = -40c to +85c. v cca direction v ccb units 4.5 to 5.5v 3.0 to 3.6v 2.3 to 2.7v 1.65 to 1.95v min. min. min. min. 4.5v to 5.5v a to b 50 50 40 30 mhz b to a 50 50 40 40 3.0v to 3.6v a to b 50 50 40 19 mhz b to a 50 50 40 40 2.3v to 2.7v a to b 40 40 30 19 mhz b to a 40 40 30 30 1.65v to 1.95v a to b 40 40 30 19 mhz b to a 30 30 19 19 notes: 13. f-toggle guaranteed by design simulation; not production tested.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 11 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications ac characteristics output load: c l = 50pf, r pu = 2.2k , and t a = -40c to +85c. symbol parameter v ccb units 4.5 to 5.5v 3.0 to 3.6v 2.3 to 2.7v 1.65 to 1.95v typ. max. typ. max. typ. max. typ. max. v cca = 4.5 to 5.5v t plh a to b 1 3 1 3 1 3 1 3 ns b to a 1 3 2 4 3 5 4 7 t phl a to b 2 4 3 5 4 6 5 7 ns b to a 2 4 2 5 2 6 5 7 t pzl oe to a 4 5 6 10 5 9 7 15 ns oe to b 3 5 4 7 5 8 10 15 t plz oe to a 65 100 65 105 65 105 65 105 ns oe to b 5 9 6 10 7 12 9 16 t skew a port, b port (14) 0.50 1.50 0.50 1.00 0.50 1.00 0.50 1.00 ns v cca = 3.0 to 3.6v t plh a to b 2.0 5.0 1.5 3.0 1.5 3.0 1.5 3.0 ns b to a 1.5 3.0 1.5 4.0 2.0 6.0 3.0 9.0 t phl a to b 2.0 4.0 2.0 4.0 2.0 5.0 3.0 5.0 ns b to a 2.0 4.0 2.0 4.0 2.0 5.0 3.0 5.0 t pzl oe to a 4.0 8.0 5.0 9.0 6.0 11.0 7.0 15.0 ns oe to b 4.0 8.0 6.0 9.0 8.0 11.0 10.0 14.0 t plz oe to a 100 115 100 115 100 115 100 115 ns oe to b 5 10 4 8 5 10 9 15 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns v cca = 2.3 to 2.7v t plh a to b 2.5 5.0 2.5 5.0 2.0 4.0 1.0 3.0 ns b to a 1.5 3.0 2.0 4.0 3.0 6.0 5.0 10.0 t phl a to b 2.0 5.0 2.0 5.0 2.0 5.0 3.0 6.0 ns b to a 2.0 5.0 2.0 5.0 2.0 5.0 3.0 6.0 t pzl oe to a 5.0 10.0 5.0 10.0 6.0 12.0 9.0 18.0 ns oe to b 4.0 8.0 4.5 9.0 5.0 10.0 9.0 18.0 t plz oe to a 100 115 100 115 100 115 100 115 ns oe to b 65 110 65 110 65 115 12 25 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns v cca = 1.65 to 1.95v t plh a to b 4 7 4 7 5 8 5 10 ns b to a 1.0 2.0 1.0 2.0 1.5 3.0 5.0 10.0 t phl a to b 5 8 3 7 3 7 3 7 ns b to a 4 8 3 7 3 7 3 7 t pzl oe to a 11 15 11 14 14 28 14 23 ns oe to b 6 14 6 12 6 12 9 16 t plz oe to a 75 115 75 115 75 115 75 115 ns oe to b 75 115 75 115 75 115 75 115 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns note: 14. skew is the variation of propagation delay betw een output signals and applies only to output signals on the same port (a n or b n ) and switching with the same polarity (low-to-high or high-to-low) (see figure 15) . skew is guaranteed, but not tested.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 12 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications capacitance t a = +25c. symbol parameter conditions typical units c in input capacitance control pin (oe) v cca = v ccb = gnd 2.2 pf c i/o input/output capacitance, a n , b n v cca = v ccb = 5.0v, oe = gnd, va = vb = 5.0v 13.0 pf c pd power dissipation capacitance v cca = v ccb = 5.0v, v in = 0v or v cc , f = 400khz 13.5 pf figure 8. ac test circuit table 1. propagation delay table test input signal output enable control t plh , t phl data pulses v cca t pzl (oe to a n , b n ) 0v low to high switch t plz (oe to a n , b n ) 0v high to low switch table 2. ac load table v cco c l r l 1.8 0.15v 50pf 2.2k 2.5 0.2v 50pf 2.2k 3.3 0.3v 50pf 2.2k 5.0 0.5v 50pf 2.2k
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 13 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications timing diagrams v cci v cco gnd data in data out t pxx t pxx v mi v mo data out output control t pzl v mi v cc a v ol gnd v y figure 9. waveform for inverting and non-inverting functions (15) figure 10. 3-state output low enable time ( 15 ) data out output control t plz v mi v cca v ol gnd v x symbol v cc v mi (16) v cci / 2 v mo v cco / 2 v x 0.5 x v cco v y 0.1 x v cco figure 11. 3-state output high enable time (15) figure 12. active output rise time figure 13. active output fall time v cci v cci /2 v cci /2 gnd data in t period f-toggle rate, f = 1 / t period v cco v mo t skew t skew v mo gnd data output t skew = (t phlmax ? t phlmin ) or (t plhmax ? t plhmin ) v cco v mo v mo gnd data output figure 14. f-toggle rate figure 15. output skew time notes: 15. input t r = t f = 2.0ns, 10% to 90% at v in = 1.65v to 1.95v; input t r = t f = 2.0ns, 10% to 90% at v in = 2.3 to 2.7v; input t r = t f = 2.5ns, 10% to 90%, at v in = 3.0v to 3.6v only; input t r = t f = 2.5ns, 10% to 90%, at v in = 4.5v to 5.5 only. 16. v cci = v cca for control pin oe or v mi = (v cca / 2).
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 14 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications physical dimensions (0.09) (0.1) (0.2) 1.6 2x 0.05 0.00 1.6 2x c 0.05 c 4 3. drawing conforms to asme y.14m-1994 2. dimensions are in millimeters 1. package conforms to jedec mo-255 variation uaad bottom view 4. pin 1 flag, end of package offset mac08arev4 1 23 5 6 7 8 notes: 8x 0.25 0.35 3x 8x 1.0 4 0.5 8x 0.25 0.15 0.10 cab 0.05 c 0.10 c top view index area b recommended landpattern a 0.10 c 0.55 max 0.05 c detail a 0.35 0.25 (0.15) (0.20) 0.35 0.25 detail a pin #1 terminal scale: 2x 5. drawing file name: mkt-mac08arev4 figure 16. 8-lead micropak?, 1.6mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape & reel format for micropak? always visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 15 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications physical dimensions 1.20 1.4 5 2 0.35 0.25 7x (0.2) 0.15 0.25 seating plane 0.40 0.10 cab 0.05 c 2x 2x 0.025 0.00 c 0.10 a c 0.10 a. does not conforms to jedec standard. c 0.05 b c 0.05 pin#1 ident 0.55 max c bottom view top view 8 1 6 4 notes: b. dimensions are in millimeters. c. dimensions and tolerances conforms to asme y14.5m, 1994. d. drawing file name : umlp08arev1 8x detail a detail: a scale : 2x 0.30 0.20 0.10 45 0.10 0.400 0.250 8x 0.350 7x 0.450 1.250 0.625 1.450 0.725 figure 17. 8-lead ultrathin mlp, 1.2mm x 1.4mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape & reel format for micropak? always visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/dwg/um/umlp08a.pd f.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fxma2102 ? rev. 1.0.2 16 fxma2102 ? dual-supply, 2-bit voltage translat or / buffer / repeater / isolator for i 2 c applications

▲Up To Search▲

Price & Availability of FXMA2102UMX

	To Download FXMA2102UMX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .